Data buses are used in integrated circuits (ICs) to transfer data between master devices, such as user-controlled microprocessors, and slave devices that control peripheral devices, such as memories or the like. To avoid overlapping data messages that may lead to error in data transmission between the master and slave devices, it is common to employ an arbiter to arbitrate message traffic on the bus. One such bus design is an Advanced High-performance Bus (AHB) from ARM Limited of Cambridge, England. The AHB bus design is a form of an Advanced Microcontroller Bus Architecture (AMBA). The AHB bus provides high performance, high clock frequency data transfer between multiple bus master devices and multiple bus slave devices through use of an arbiter. The AHB bus is particularly useful in integrated circuits, including single-chip processors, to couple the processors to on-chip memories and to off-chip external memory interfaces.
Many bus designs, including the AHB bus, are capable of single data word transfers and bursts of multiple data words between the master and slave devices. Each data transfer includes an address and control cycle, which is followed by one or more data cycles. During the address and control cycle, the master device transmits the address for the next data transfer and control signals providing information such as the transfer type, the direction of the transfer (read or write), the size of the transfer, whether the transfer is a single transfer or a burst of multiple transfers. In the case of a burst, the control signals indicate the type of burst. For example in the AMBA AHB bus, several types of burst can be specified such as 4, 8 and 16-beat bursts and bursts of unspecified length.
In some bus designs, the master device can selectively stall transfers in the middle of a burst if the master device is not ready for further transfers. For example on an AHB bus, a master device can initiate a “BUSY” transfer type in the middle of a burst to insert one or more idle cycles during the burst. The BUSY transfer type is sent to the slave device to indicate that the master device is continuing with a burst of transfers, but the next transfer cannot take place immediately. In response to a BUSY transfer type, the slave device must stall subsequent transfers of data words in the burst until the master device is ready to continue with further transfers.
These operations are handled by interface circuitry in the slave device, which is configured to implement the bus protocol. These interface circuits can become very complex and difficult to design, particularly for complex protocols and operations such as master-induced stalls in the middle of burst-type transfers. Although simplified protocols exist for many bus designs, including an AHB-LITE protocol that implements a subset of the full AHB bus protocol, these simplified protocols have not reduced the difficulty of implementing master-induced stalls during burst-type transfers.
Simplified interface circuits are therefore desired that are capable of maintaining full compliance with the bus protocol but reduce the complexity in accommodating master-induced stalls during burst-type transfers.